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| April 03, 2006 | EE Times |
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| Cisco Teams With Cortina Systems to Challenge Interconnect Industry |
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| Portfolio Company: Cortina Systems |
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San Jose, Calif. -- In a surprise move, Cisco Systems Inc. and startup Cortina Systems Inc. will release an interconnect protocol today that they hope will be broadly used to link communications chips at data rates of 20 Gbits/second and beyond. But their Interlaken technology will be incompatible with a similar effort in a late stage of development at the Network Processing Forum, a group of about 30 silicon and systems developers.
The clash comes at a time when several initiatives are chasing multigigabit chip-to-chip links. Where Interlaken and NPF's Scalable-SPI spec are packet interfaces designed for a communications system's data plane, the other efforts--including RapidIO, PCI Express and HyperTransport--are typically aimed at control plane applications. The upshot of all those efforts will be a migration over the next few years from today's individual 1- to 2.5-Gbit/s serial-lane interconnects to far speedier links.
Engineers at Cisco saw that the 10-Gbit/s System Packet Interface-4.2, which requires 80 pins, could not keep pace with the rise of 10-Gbit Ethernet switches and systems using 80-Gbit/s or faster backplanes. "In our road map discussions with vendors, this problem kept cropping up," said Mark Gustlin, a technical lead in Cisco's Service Provider Routing Group.
More than a year ago, engineers from Cisco and Cortina found they were both working on a similar packet interface and decided to collaborate. The result is Interlaken, a pro- tocol for migrating the logical structures of SPI-4.2 onto a serdes transport based on the Optical Internetworking Forum's Common Electrical Interface standard. Using a 6.25-Gbit/s serdes, Interlaken slashes pin counts to just eight for a 10-Gbit/s link.
The spec acts as a framework that engineers can employ over serdes running from 3.125 to 10 Gbits/s across any number of parallel lanes. It could be used to connect a network processor with framer, traffic-management and port-aggregation chips on a line card, or to link those chips to a system backplane.
That's very similar to the Scalable-SPI spec the Network Processing Forum has been working on since June 2004. NPF started the SSPI effort as part of a collaborative agreement with the Optical Internetworking Forum (OIF), a broader group of about 80 carriers and OEMs.
About eight chip makers are going through what could be a final cleanup phase of the SSPI spec, though no exact release date has been set. Because it is still under development, details of SSPI remain under nondisclosure.
The good news is that the Interlaken and SSPI principals have just begun talking to each other, although it is too early to tell what may come of the discussions. The two sides are likely to find a number of interoperability issues as they take a detailed look at each other's specs.
Encoding split
To enhance system reliability, Cisco and Cortina chose a nonstandard 64B/67B encoding scheme that breaks compatibility with the 64B/66B approach. The latter is used in existing 10G Ethernet and framer chips and was adopted by SSPI.
"The extra bit allows us to more closely control dc balance," said Cisco's Gustlin. "In addition, we use a different scrambler than the standard 64/66 scrambler in order to prevent error multiplication.
"These changes make [Interlaken] incompatible with standard 64/66."
The encoding approach enables other capabilities. An inversion feature can flip the bits in a channel that has been determined to be in or near an error state. Interlaken also supports a MetaFrame feature that can shut down a lane that is failing and set up a redundant pathway.
"Both OIF and NPF felt it was mandatory that 64B/66B be preserved" to maintain compatibility with existing phase-locked-loop and oscillator blocks, said Mike Lerer, a consultant to Xilinx Inc. who chairs NPF's hardware working group overseeing SSPI. "That turned out to be a good choice, because the upcoming IEEE backplane Ethernet standard has also adopted 64/66.
"If Cisco and Cortina had better ideas, they would have been welcome to express them to the people in this project," said Lerer, who also chaired the OIF group that defined SPI-4.2.
"There are all these blocks out there using 64/66. They are quite difficult to make and end up costing a fair amount of money," said Brian Holden, an NPF board member. Neither Holden nor Lerer had heard of the Interlaken effort until told about it by EE Times.
Cisco's deviation with Interlaken is "so bizarre. It's such a minor improvement," said Tom Cox, executive director of the RapidIO Trade Association. RapidIO is primarily focused on handling control information rather than the raw packet data flows that pass over SPI-4.2. Cox said he thought the SSPI effort was making adequate progress toward completing its spec.
"I don't see the encoder as the most complicated part of a chip that will be designed with [the Interlaken] protocol," countered Cisco's Gustlin.
Some fear that Interlaken represents an attempt to put other system and chip makers at a disadvantage.
"Their move to 64/67 encoding sounds like it could be a thinly veiled ploy to perpetuate a proprietary interface that Cisco has more direct control over [than something from] the NPF," said a senior engineer in a comms systems company that competes with Cisco.
"In my experience, a correctly designed interconnect channel has enough signal integrity margin--even at 10-plus Gbits/s--to avoid the need for any more aggressive error control than 64/66 of- fers," said the engineer, who asked not to be identified. "I believe most telecom OEMs will prefer a truly standards-based solution, and that is the message I will be sending to my chip and board suppliers."
In the relatively small comms chip sector, standards interoperability is typically handled in an ad hoc fashion. Vendor-to-vendor efforts, rather than formal compliance-testing mechanisms, are the norm.
"What Cisco does matters, and they have a lot of knowledge in this area," said Holden of NPF.
In the past, OIF and NPF let vendors work out interoperability issues on their own, Holden said. "With SPI-4.2, it took several rounds of implementations to get everything interoperable. That's likely to be the case for any new standard in this area," he said.
Cisco and Cortina say they will make the Interlaken technology available royalty free in hopes that other system and chip makers will adopt it as an ad hoc standard that's ready to go today. The duo wants to re-create the model of the SGMII copper physical-layer interface defined by Cisco and adopted by the industry.
"We thought it would be faster to work on it together and then release it" rather than go through a formal standards group, said Jim McKeon, a product manager at Cortina (Sunnyvale, Calif.). "A lot of people are interested in this, but most of them want to see someone else take the first steps--they just want an out-of-the-box solution."
The two companies surveyed the industry more than a year ago when they started their work, but found no significant efforts under way to upgrade SPI-4.2, Gustlin said. While they had heard of the SSPI effort, neither Cisco nor Cortina were NPF members, and they had heard no public news about progress on that standard, he added.
McKeon said Cortina plans to release its first chips using Interlaken in the fourth quarter. They will likely be follow-ons to a 24-port Gigabit Ethernet port-aggregation chip the company is now sampling.
The privately held Cortina makes a range of comms chips, including Sonet framers and media-access controllers. It has raised $85 million in three rounds of venture capital funding to date. In February 2005, the company acquired Azanda Network Devices, a maker of ATM and traffic-management chips that, like Cortina, had design activity at Cisco.
Beyond encoding, Interlaken and SSPI differ in a number of other ways. For example, Interlaken does not use forward error correction, whereas SSPI considers FEC one of its key technical planks for improving performance in the backplane. That's an application area that is primary for SSPI but tangential for Interlaken.
In addition, Interlaken appears to treat flow control in a slightly different manner than is typical in Ethernet, said Jag Bolaria, an analyst with The Linley Group (Mountain View, Calif.), who was briefed on the Interlaken technology.
Cortina has a bus-functional model of Interlaken in configurable Verilog RTL code to emulate the interface for testing. But the company has not decided whether to release it. "My impression was that they haven't thought [the interoperability issues] through yet," said Bolaria.
'Lunatic fringe'
Meanwhile, a number of control interface initiatives are preparing to push their approaches into the 5- to 6-Gbit/s range starting this summer, although most of them appear to be well in advance of mainstream demand.
"There's a lunatic fringe of applications pursued by people in the military and elsewhere who just can't get enough performance, and they want 5 and 6 Gbits/s now," said Cox of the RapidIO group. The consortium will release its higher-speed specs this summer but does not expect products based on them to become widely available for two to three years.
The PCI Special Interest Group decided more than a year ago that its next leap would be from 2.5 to 5 Gbits/s. With its electrical specs basically finished, the group is reviewing the implications for 5-Gbit/s signals on all the various kinds of products where Express is used, tightening up specifications as needed to provide adequate margins for error. The group expects its 5-Gbit work will largely be wrapped up by September. Graphics chips will be among the first users, so that they can collapse the 16-lane Express interconnects on today's devices to fewer channels, saving pins and die area.
The Advanced Switching Interconnect, a variant of PCI Express for embedded systems such as communications routers and switches, will adapt its protocol to ride the faster Express lanes, said Rajeev Kumar, an Intel Corp. manager who heads the ASI Special Interest Group.
The HyperTransport Consortium is also on the cusp or releasing version 3.0. The revision doubles the bandwidth of its parallel interconnect spec, which is aimed at linking microprocessors. |
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